Although single crystal silicon wafers have been mainly used as semiconductor substrates, they have been becoming incompatible with devices such as LED-related devices and highly efficient power devices containing next-generation semiconductor substrates.
In particular, under the circumstances that require higher proof pressure (improvement in dependability) and lower ON resistance (reduction in loss), semiconductor devices comprising various compound semiconductors including SiC, substrates of sapphire- or ceramic type have been developed and mass-produced.
Among them, SiC and GaN, as compared with Si, have a large wideband gap and are operable under high temperatures (Si operates at 175° C. whereas SiC operates at 200 to 300° C.). Further, SiC and GaN are capable of achieving low resistance because their dielectric breakdown field strength is more than 10 times of that of Si. Therefore, SiC and GaN are expected to be mainly used in the near future instead of the silicon.
Wafer materials with high hardness, such as monocrystal and polycrystal materials (SiC, sapphire, others), are required to be highly flattened as well as have high quality surface. In such cases, these materials are generally subjected to several lapping and polishing processes (e.g., lapping, rough polishing, middle polishing, final polishing, etc.) before finish.
Nowadays, metals such as tin, copper and iron are mainly used as a lapping platen. Moreover pads of urethane type, nonwoven fabric type, suede type, etc. are used as a polishing pad. Furthermore, loose abrasive grains, such as fine diamond abrasive grains, colloidal-silica abrasive grains, cerium sulfide abrasive grains, and alumina abrasive grains are used as abrasive grains for polishing.
However, in the case of using such wafer materials with high hardness, it is very difficult to make these materials have high flatness as well as high quality surface by lapping and polishing processes with a conventional polishing pad. Furthermore, it is known that the time required for lapping and polishing processes becomes longer in such hard wafer materials. In general, longer polishing time during the processing deteriorates yield because of difficulty in achieving high planarization and high quality surface. That is, since conventional polishing pads cannot improve polishing rate and further deteriorate in productivity, lapping and polishing systems which can raise the polishing rate are required. Moreover, since flatness control for planarizing a metal platen needs troublesome labor, the lapping and polishing system which can save labor management is required.
For example, Patent Document 1 (JP Laid-open Patent Publication No. 9-117855) discloses a polishing pad having a plurality of pores for holding abrasive materials polishing a workpiece, wherein the polishing pad has grooves on the polishing surface which polishes the above-mentioned workpiece. This reference describes application of foamed polyurethane as a hard layer of the polishing pad.
In the above-mentioned polishing pad, such grooves are effectively used for removing a semiconductor wafer from the polishing pad after polishing and make it possible to control the holding capacity of the abrasive materials.